1. Field of the Invention
The present invention relates to a method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal. In particular, the invention relates to a correlated double sampling circuit that removes low frequency noise and offset common to a signal. The correlated double sampling circuit can be used with a camcorder system to calibrate black pixels output by the charge coupled device.
2. Description of the Related Art
FIG. 1 illustrates a block diagram of a front end 20 of a CCD interface circuit which may be used for example in a camcorder system. The front end includes a charge coupled device (CCD) sensor 22 which detects and outputs an analog signal on line 24, to be processed by the camcorder. The analog signal on line 24 is fed to a correlated double sampling circuit 26 which takes a first sample and a second sample of the analog signal, which takes a difference between the first and second samples to remove low frequency noise and any offsets common to both samples of the signal, and which outputs a difference signal on line 28. The difference signal on line 28 is amplified by amplifier 30 and an amplified signal is output on line 32 to a black level correction circuit 34. The black level correction circuit 34 adds an offset level to the amplified signal on line 32 so as to calibrate the amplified signal to a desired reference level. In particular, the offset level is calibrated to substantially one end of an input range of analog-to-digital converter 38 when the charge coupled device 22 outputs a signal on line 24 corresponding to black pixels. The black pixels are intentionally added around a periphery of the CCD for the purpose of calibrating the offset level. In addition, when the analog signal output on line 24 corresponds to pixels of an image detected by the CCD, the black level correction circuit adds the calibrated offset value to the amplified signal on line 32 corresponding to the pixel image. Thus, the correlated double sampling circuit 26 and the black level correction circuit 34 together filter out low frequency noise from the analog signal output by the CCD and add the calibrated offset value to the difference signal. A resulting signal is output on line 36 to the analog-to-digital converter 38, and is converted into a digital value output on line 40. The digital value is then processed by digital signal processor 42.
FIGS. 2a and 2b show a block diagram and a timing diagram, respectively of an embodiment of the correlated double sampling circuit 26 of FIG. 1. As discussed above, the correlated double sampling circuit is used to remove low frequency noise and offsets from an analog signal. In particular, it is used at the output of the CCD device 22 because it can remove several kinds of noise, e.g., reset noise from CCDs which result because the CCD doesn't always reset to exactly the same value and flicker (1/f) noise of the CCD. A basic principle of the circuit is that the first and second samples are taken of the analog signal output from a single channel of the CCD device, a first sample is taken with the analog signal at the reset level and a second signal is taken with the pixel data level signal included in the analog signal. A difference between the two samples is then taken so that any noise or offset common to both samples is removed from the difference of the two samples.
More specifically, the correlated double sampling circuit 26 of FIG. 2a includes a first sample-and-hold circuit 44, a second sample-and-hold circuit 46 and third sample-and-hold circuit 48. Referring to the timing diagram of FIG. 2b, the first sample-and-hold circuit is responsive to clock signal Q1 so that on a falling edge 50 of the clock signal Q1, the first sample is taken of the analog signal at the reset level on line 24. In the camcorder system of FIG. 1, the correlated double sampling circuit takes advantage of a known condition of the CCD circuit 22. In particular, the CCD circuit is always reset before a new pixel is measured. The CDS circuit of FIG. 2a takes advantage of this existing condition by sampling the signal at the output line 24 of the CCD circuit during this reset phase, before the new pixel information appears. Thus, in response to the falling edge 50 of the clock signal Q1, the first sample of the signal on line 24 represents the reset level of the signal from the CCD circuit 22. On a falling edge 52 of clock signal Q2, the first sample is clocked into the second sample-and-hold circuit 46 and at the same time, the third sample-and-hold circuit 48 takes the second sample of the analog signal having the new pixel information on line 24. The second sample is a data level sample of an intensity of the new pixel information signal output by the CCD circuit 22. The first sample and the second sample are output to difference element 54 which performs a difference operation on the first and second samples and provides the difference signal on line 28 free of any noise or offset that is common to both samples.
However, one problem with the circuit of FIG. 2a is that a time period for which the filtered signal on line 28 is valid is not a complete period of the pixel information signal on line 24. According to this disclosure it is to be understood that a pixel period is defined as a time period between falling edge transitions of the clock signal Q.sub.2, and includes times for which the analog signal at the reset level and the analog signal at the data level are present on line 24. For the circuit of FIG. 2a, as the clock signal Q2 transitions to the high state, the sample and hold-circuit 48 is in acquisition mode and the output of the circuit on line 28 is no longer valid. Thus, the period for which the difference signal on line 28 is valid is not a full pixel period. For example, if the clock signal Q.sub.1 and Q.sub.2 have a 50% duty cycle of the pixel period, the period for which the difference signal is valid is only half of the pixel period.
In addition, another problem with the circuit of FIG. 2a is that the sample-and-hold circuit 46 is driven by the sample-and-hold circuit 44. Consequently capacitors of the sample-and-hold circuit 46 must either be relatively small which results in a noisy signal output by the circuit 26, or if the capacitors are relatively large, the sample-and-hold-circuit 44 must supply enough power to drive the capacitors which in turn has to be dissipated in the circuit 26.
FIG. 3 illustrates the correlated double sampling circuit 26 of FIG. 2a together with two feedback circuits to form an input clamping circuit 180. The operation of the correlated double sampling circuit 26 is as discussed above with respect to FIG. 2. The input clamping circuit includes feedback circuits 182 and 184 which are provided to level shift a voltage of the signal on line 24 to within a supply range and operating range of the circuit 180. For example, a voltage on the line 24 may be 10 volts, but the circuit 180 may operate off of a 5 volt supply. Therefore, there is a need to clamp the voltage at the input to the correlated double sampling circuit 26 to within an operating range of the correlated double sampling circuit. The feedback circuits 182 and 184 clamp the input voltage on lines 186 and 188 to the desired voltage selected to be within the operating range of the circuit 180.
FIG. 4 illustrates a block diagram of an embodiment of the black level correction circuit 34 of FIG. 1. As described above, the signal output by the CCD circuit 22 on line 24 is processed by the correlated double sampling circuit 26 and the resulting difference signal on line 28 is passed to the programmable amplifier 30. An offset value on line 56 is added to the amplified signal on line 32 at summing block 58. The resulting signal output from the summing block on line 36 is then digitized by the analog to digital converter 38. One purpose of the black level correction circuit is to calibrate the value of the offset signal on line 56 so as to reference the resulting signal on line 36 substantially to one end of the input range of the analog-to-digital converter. For example, the amplified signal on line 32 may be in a range from 0 to 1 volt, and the offset level on line 56 may be added to adjust the resulting signal range from -0.5 volts to +0.5 volts. The black pixels are intentionally provided around the periphery of the CCD circuit 22 for this particular purpose. More specifically, when the signal on line 24 corresponding to the black pixels is input to the black level correction circuit 34, the switch 62 is biased to a closed position to provide a closed feedback loop including summing block 64 and integrator 66, so that the signal on line 36 is fed back to the summing block 58 as the offset value on line 56. The feedback loop including the integrator 66 and the summing block 64, compares the signal on line 36 to a negative reference value on line 68 and clamps the offset level on line 56 to the correct level to reference the signal on line 36 to the negative reference value on line 68. In addition, when the analog signal on line 24 corresponds to the data level of the intensity of the new pixel information signal, the switch 62 is biased to an open position so that the integrator holds the calibrated offset level and the calibrated offset level value is added to the amplified signal on line 32 corresponding to the intensity of the new pixel information signal.
However, one problem with the black level correction circuit of FIG. 4 is that the programmable amplifier 30 may saturate under high gain conditions where the filtered signal on line 28 has only modest errors, or when the programmable gain amplifier 30 has modest input referred offsets. For example, if the camcorder system of FIG. 1 is operated on a 3 volt supply, if the analog-to-digital converter 38 has a +/-0.5 volt signal dynamic range at its input, and if the programmable amplifier has a gain of 50, an offset value of 10 millivolts will be amplified by the programmable amplifier 30 and the amplified signal on line 32 will be at 0.5 volts, thus saturating the input range of the analog-to-digital converter. In addition, another problem with the circuit of FIG. 4 is that the programmable amplifier 30 has a limited linear operating range. In particular, the circuit of FIG. 4 is a differential system having a zero point which does not change with gain of the programmable amplifier, and which is at mid-scale of the amplifier's linear operating range. Accordingly, only half of the amplifier's linear operating range is used.
Accordingly, it is an object of the present invention to improve upon the correlated double sampling circuit, the black level correction circuit, and the input clamping circuit of the related art.